In the field of semiconductor memory devices, three-dimensionally stacked memory for which higher integration is possible with relatively no constraints due to the limits of the resolution of lithography is drawing attention. Such a three-dimensionally stacked memory includes, for example, memory strings disposed two-dimensionally in a matrix configuration, where the memory string includes: a semiconductor pillar having a columnar configuration; a tunneling layer, a charge storage layer, and a blocking layer stacked to cover the side surface of the semiconductor pillar; and multiple electrode films provided at a prescribed spacing in the stacking direction to intersect the semiconductor pillar.
In such a three-dimensionally stacked memory, electrons are trapped inside the tunneling layer when a programming/erasing operation is repeatedly performed. Then, there is a risk that reliability of the data retention characteristics may be lost when the trapped electrons are de-trapped.